1. Field
This patent specification relates to a method and apparatus for bus arbitration, and more particularly to a method and apparatus for bus arbitration that effectively alters a priority order for simultaneous bus use requests.
2. Description of Related Art
Conventionally, a bus arbitration apparatus for use in apparatuses such as one having a plurality of DMA (direct memory access) circuits, a multi-processor system having a plurality of CPUs (central processing units), and the like performs an arbitration operation against a plurality of simultaneous requests for use of a system bus from the plurality of DMAs or CPUs in accordance with a fixed priority order. As a result of the arbitration operation, the bus arbitration apparatus provides a permission to use the system bus to the requester determined as having the highest priority based on the fixed priority order. The above-mentioned system bus is typically compatible with devices conforming to an OHCI (open host computer interface) standard of IEEE (Institute of Electrical and Electronics Engineers).
For example, a system having four DMA circuits such as DMA-A, DMA-B, DMA-C, and DMA-D and a single system bus is considered. If this system is provided with a fixed priority order of A>B>C>D, the DMA-A is assigned the highest priority and the DMA-D is assigned to the lowest priority. When the four DMAs simultaneously raise requests for use of the system bus, the system needs to arbitrate the simultaneous requests and conducts an arbitration operation in accordance with the fixed priority order. This method, however, has a drawback. If the DMA-A, DMA-B, and DMA-C continuously raise the bus use request at the same time the DMA-D raises the request, the DMA-D will never have a chance since the DMA-D has the lowest priority.
To attempt to solve the above-described drawback of the fixed priority order method, an arbitration apparatus having a round robin method has been developed. In the round robin method, the priority order is shifted by one each time a plurality of bus use requests are simultaneously raised. More specifically, shifting the priority order means that an initial priority order of A>B>C>D is in turn changed to orders of B>C>D>A, C>D>A>B, D>A>B>C, A>B>C>D, and so on. With this method, the above-described drawback of the fixed priority order could be reduced. In an actual system operation, each DMA independently raises the bus use request and it is rare that the DMAs raise their requests at intervals of an even time period. Accordingly, it may happen that a certain DMA always raises the request at the same time a higher priority DMA raises the request even in the bus arbitration apparatus using the round robin method. In this case, the certain DMA is continuously not given a bus use permission.